Fractional-n Frequency Synthesizers

At the Microsystems Technology Laboratory at MIT, we have developed two techniques that allow fast and accurate simulation of both dynamic and noise performance of fractionalN synthesizers at a detailed behavioral level. We incorporated these techniques into a custom C++ program to simulate the dynamic and noise performance of a prototype Σ-∆ frequency synthesizer. This class of fractional-N synthesizers dithers the divide value according to the output of a Σ∆ modulator.1 Such dithering ensures high frequency resolution,1 but also has the negative effect of introducing quantization noise, which degrades the overall phase-locked loop (PLL) noise performance. It can be very helpful to simulate the effects of this quantization noise, along with other noise sources (shown in Figure 1b) in the PLL, on overall PLL performance. Simulating the synthesizer’s dynamic response to variations of the Σ-∆ input can also help evaluate stability and characterize the system’s performance when it is used as a transmitter.2